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Analog Demultiplexer Operating at up to 200 GS/s Using Four Time Interleaved Switched Emitter Followers with a 50% Duty Cycle Clock | IEEE Conference Publication | IEEE Xplore

Analog Demultiplexer Operating at up to 200 GS/s Using Four Time Interleaved Switched Emitter Followers with a 50% Duty Cycle Clock


Abstract:

This paper presents the design and experimental results of a voltage mode analog demultiplexer (ADeMUX) that uses four time interleaved switched emitter follower track-an...Show More

Abstract:

This paper presents the design and experimental results of a voltage mode analog demultiplexer (ADeMUX) that uses four time interleaved switched emitter follower track-and-hold (T/H) circuits. The preamplifiers and sampling cores are linearized for ultra-broadband operation. With the utilized 90-nm SiGe-BiCMOS technology offering 300 GHz fT and 480 GHz fmax, we are able to operate the ADeMUX with up to 4 x 50 GS/s = 200 GS/s - the highest reported sampling rate to date. Compared with the state-of-the-art current mode ADeMUX circuits, the presented device offers an increase in sampling rate of more than 50%. At 128 GS/s, the chip shows the highest input bandwidth of more than 50 GHz and a linearity of more than 3 bit. This ultra-broadband analog time interleaver can be used to feed four analog-to-digital converters in CMOS technology, due to the reduced bandwidth requirement of only 16 GHz for operation at 128 GS/s or 25 GHz for 200 GS/s.
Date of Conference: 05-08 December 2021
Date Added to IEEE Xplore: 25 January 2022
ISBN Information:
Conference Location: Monterey, CA, USA

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