High-Speed TLP and ESD Characterization of ICs | IEEE Conference Publication | IEEE Xplore

High-Speed TLP and ESD Characterization of ICs


Abstract:

Electrostatic discharge is always an area of concern in reliability and production of ICs. To design effective ESD clamps, knowing how the clamp turns on and operates dur...Show More

Abstract:

Electrostatic discharge is always an area of concern in reliability and production of ICs. To design effective ESD clamps, knowing how the clamp turns on and operates during an ESD event is critical. This cannot be done with S-parameters or any other type of typical RF characterization. Transmission Line Pulsing, TLP, is a high-speed system that mimics an ESD event with a very short flat pulse (100 ns is typical). This allows in situ measurement of the voltage and current at the DUT during an ESD-like event. This paper will give an introduction into the theory (which is based on time domain reflection), configuration and uses of TLP. Different TLP configurations will be reviewed, and each configuration an IV curve for the DUT response is discussed. Calibration and correction will be explained which are done in the time domain. These provide the voltage and current references. The importance of the TLP load line will be discussed and its application to DUT characterization of turn-on and snap-back. Finally, characterization with pulses shorter than 10 ns, Very Fast TLP, are presented and its hurdles to accurate calibration.
Date of Conference: 05-08 December 2021
Date Added to IEEE Xplore: 25 January 2022
ISBN Information:
Conference Location: Monterey, CA, USA

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