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A CMOS neurostimulator with on-chip DAC calibration and charge balancing | IEEE Conference Publication | IEEE Xplore

A CMOS neurostimulator with on-chip DAC calibration and charge balancing


Abstract:

A multi-channel biphasic neural stimulator with on-chip DAC calibration and current matching capabilities is presented. Each channel consists of two sub-binary radix DACs...Show More

Abstract:

A multi-channel biphasic neural stimulator with on-chip DAC calibration and current matching capabilities is presented. Each channel consists of two sub-binary radix DACs, for the anodic and cathodic stimulation phases, and a wideswing high output impedance current source and sink. A single integrator is shared among channels and serves to calibrate DAC coefficients and to closely match the anodic and cathodic stimulation phases. After calibration, the differential non-linearity is bounded between +/- 0.5 LSBs at 8-bit resolution, and the two stimulation phases can be matched to better than 50 nA. We demonstrate operation with stimulation through a tungsten microelectrode in saline, and show stimulator induced modulation of neural activity in the cortex of a rat. Our novel architecture allows for blind self-calibration, amenable to implantable neural interfaces.
Date of Conference: 31 October 2013 - 02 November 2013
Date Added to IEEE Xplore: 12 December 2013
Electronic ISBN:978-1-4799-1471-5
Print ISSN: 2163-4025
Conference Location: Rotterdam, Netherlands

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