We report the design, implementation, and experimental characterization of an EEG recording active electrode (AE) architecture that features analog in-AE common-mode rejection ratio (CMRR) improvement. Detailed system-level architecture and circuit implementation of the proposed AE is presented following a brief analytical and comparative review of the effect of gain and electrode impedance mismatch on CMRR degradation in state-of-the-art AE-based wearable EEG recording systems. An active electrode integrated circuit (IC) based on the proposed CMRR-enhancing architecture is fabricated in a 180nm CMOS technology and is experimentally characterized. Our measurement results show a CMRR of 82.2dB (at 60Hz), amplification voltage gain of 52.8dB, a bandwidth of 0.2-400Hz, ±350mv input DC offset tolerance, and 0.66µv integrated input referred noise (0.5-100Hz), while consuming 13.5µW per channel. An EEG recording has been performed using the developed AE IC connected to active electrodes placed on the forehead.