With the advancement of modern technology, the Internet of Things (IoT) has become widespread and has increased convenience for users. However, many IoT systems have vulnerabilities, and therefore are attractive targets for attackers. Researchers have proposed the use of hardware for attack detection as a security mechanism that can be incorporated into IoT devices. A method that integrates attack detection and communication detection into a single mechanism, allowing for a more compact implementation compared to dedicated implementations of each function, was proposed. Herein, we design and implement circuits for this mechanism by using the hardware description language Verilog-HDL. This approach allows us to evaluate the circuits in an environment that is closer to hardware. Additionally, to conduct experiments in an environment that is more representative of the IoT environment compared to that used in the previous study, we perform feature selection and reduce discriminator size to miniaturize the circuit. As the evaluation metric, we calculate the circuit size of the discriminator implemented using Verilog-HDL. This facilitates more accurate assessment of the circuit size compared to the evaluations conducted in previous works. In conclusion, despite a reduction in discriminator size, the accuracy of the proposed mechanism was comparable to that of dedicated implementations of attack detection mechanisms, and its circuit size was smaller.