Abstract:
GAM, TPN and AWE methods have been accepted by many researchers as methods of modeling on chip interconnects as RC, and RLC circuits. In this paper a platform to generate...Show MoreMetadata
Abstract:
GAM, TPN and AWE methods have been accepted by many researchers as methods of modeling on chip interconnects as RC, and RLC circuits. In this paper a platform to generate the T and Π configurations for RC, RLC and RLCG models based on GAM, TPN and AWE methods is proposed. With the Π configuration of AWE based RLC model provides the best performance, this model has been mapped to an equivalent simple RC model. This improved RC model has been utilized for buffer insertion, which caused interconnect delay to be reduced and the number of buffers and their sizes to be lowered.
Date of Conference: 08-11 May 2011
Date Added to IEEE Xplore: 29 September 2011
ISBN Information: