In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of D³L family structure is presented. Performance of the circuit is evaluated and presented at different simulation corners. The results show that, compared with its dynamic version, the proposed circuit has lower power consumption and higher speed. Latency of the divider is equal to 10 half clock cycles. The circuit is designed in TSMC_180 nm CMOS process.