This paper focuses on the production testing of current mode logic gates using the 45nm technology. Two-input elementary gates are studied assuming five faults per transistor. It is shown that two different implementations of the same logic function might result in different minimum test sets depending on the transistor level architecture. In addition, in MCML gates, it is observed that the detection of faults in the upper PMOS load transistors is time dependent and that the test vectors that detect faults in the logic network also detect faults in the load transistors as well as the tail NMOS transistor.