To guarantee its safety, the power delivery network (PDN) must undergo a sequence of verification steps throughout the integrated circuit (IC) design flow. This involves checking that the voltage fluctuations in the grid remain within some user-specified safety threshold. Typically, this is done by performing a transient simulation of the grid under certain input current traces. Existing simulation tools require solving a large number of linear systems, making the tools slow for modern power grids containing billions of nodes. We propose a new simulation based approach for RC power grid verification that generates envelope upper bound waveforms on the true voltage drop waveforms. The envelope waveforms capture the peaks of the voltage drops quite accurately while requiring a much smaller number of system solves than traditional tools.