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Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier | IEEE Conference Publication | IEEE Xplore

Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier


Abstract:

This paper presents the design of pipelined IEEE 754-2008 decimal floating-point (DFP) multipliers targeting FPGAs. A key component of the architecture is the fixed-point...Show More

Abstract:

This paper presents the design of pipelined IEEE 754-2008 decimal floating-point (DFP) multipliers targeting FPGAs. A key component of the architecture is the fixed-point multiplier function which impacts the overall performance and area utilization. In this paper, we propose a new method to realize this operation by carefully organizing the partial products and developing an algorithm for binary-decimal compression. The DFP multipliers with 5 to 12 pipeline stages are coded in VHDL and implemented on a Xilinx Virtex-5 FPGA. The overall design is compared with another approach based on fixed-point multipliers using a BCD-4221 compression technique. Using post layout extracted design data, our approach achieves a delay improvement in the range of 7.9% to 20.3% and an average LUT reduction of 5%.
Date of Conference: 30 April 2017 - 03 May 2017
Date Added to IEEE Xplore: 15 June 2017
ISBN Information:
Conference Location: Windsor, ON, Canada

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