With technology scaling and increasing parallelism levels of new embedded applications, multi-cores in chip-multiprocessors (CMP) has been increased. In this context, power consumption acts a critical issue concern in future CMPs with restricted of battery lifetime. For future CMPs architecting, 3D stacking of Last Level Cache (LLC) has been recently introduced as a new methodology to combat the performance challenges of 2D integration. However, the 3D design of LLCs incurs more leakage power utilization compared to conventional cache architectures in 2Ds due to dense integration. We present in this work a power-efficient reconfigurable hybrid last level cache architecture for future CMPs. The proposed hybrid architecture SRAM memory is incorporated with STT-RAM technology by using the characteristics for both new and traditional technologies. The experimental results show that the designed method minimizes power consumption under multi-programmed and multithreaded applications.