Abstract:
Inserting the n-well and p+ diffusion into the drain region of NMOS transistor, the embedded SCR NMOS (ESCR NMOS), without changing any DC I-V characteristics of NMOS, an...Show MoreMetadata
Abstract:
Inserting the n-well and p+ diffusion into the drain region of NMOS transistor, the embedded SCR NMOS (ESCR NMOS), without changing any DC I-V characteristics of NMOS, and a very low capacitance (/spl sim/50 fF) ESD protection (LCESD) device are developed successfully for output pad and input pad, respectively. In addition, a protection scheme, combining the power protection device and a n+ guard-ring, is proposed and proven to be capable of protecting four directions ESD zapping and without increasing the LCESD device capacitance.
Published in: Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)
Date of Conference: 15-15 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7250-6