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A 16 kb 1T1C FeRAM test chip using current-based reference scheme | IEEE Conference Publication | IEEE Xplore

A 16 kb 1T1C FeRAM test chip using current-based reference scheme


Abstract:

A 16 kb 1T1C FeRAM test chip is designed and fabricated in a 0.35 /spl mu/m FeRAM process. The test chip uses a reference generation scheme that balances fatigue evenly b...Show More

Abstract:

A 16 kb 1T1C FeRAM test chip is designed and fabricated in a 0.35 /spl mu/m FeRAM process. The test chip uses a reference generation scheme that balances fatigue evenly between memory cells and reference cells, hence providing the 1T1C cell with 2T2C robustness to fatigue. The test chip achieves an access time of 62 ns at 3V.
Date of Conference: 15-15 May 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7250-6
Conference Location: Orlando, FL, USA

References

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