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A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer | IEEE Conference Publication | IEEE Xplore

A dual 10b 200MSPS pipeline D/A converter with DLL-based clock synthesizer


Abstract:

A dual 10b/200MSPS pipeline digital to analog converter (DAC) suitable for communication applications is here presented. It has been designed using a 4-metal level 3.3 V ...Show More

Abstract:

A dual 10b/200MSPS pipeline digital to analog converter (DAC) suitable for communication applications is here presented. It has been designed using a 4-metal level 3.3 V 0.5 /spl mu/m BiCMOS technology and operates on a 3-phase clock synthesized by an on-chip delay locked loop (DLL). The DAC shows 9.7 effective bits and 69.4 dB of spurious free dynamic range for a synthesized sine wave of 2 Vpp at 34 MHz and output rate of 200 MSPS. The 2 DACs and DLL occupy a total area of 3 mm/sup 2/ and consume 693 mW at full-speed.
Date of Conference: 24-24 September 2003
Date Added to IEEE Xplore: 03 December 2003
Print ISBN:0-7803-7842-3
Conference Location: San Jose, CA, USA

References

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