We describe a 470 /spl mu/W 16-channel analog VLSI processor for bionic ears (cochlear implants) and portable speech-recognition front ends. The power consumption of the processor is kept at low levels through the use of subthreshold CMOS technology. Each channel is composed of a programmable bandpass filter, an envelope detector, and a logarithmic dual-slope analog-to-digital converter that currently operate over 51 dB of input dynamic range. The 16 channels were programmed to cover the entire audio frequency spectrum in a logarithmic or mel-scale fashion and sampled at 312.5 Hz with 64 discriminable levels per channel. The processor also includes an on-chip low-power microphone front end that transduces sound to an electrical signal that is input to each of the 16 channels. The processor, implemented in a 1.5 /spl mu/m process on a 9.23 mm/spl times/9.58 mm chip, with a 2.8 V supply, offers an order-of-magnitude power saving over more traditional A-to-D-then-DSP processors implemented in advanced submicron processes. It is thus suited for fully-implanted bionic ear processors of the future or portable speech-recognition front ends.