Abstract:
Programmable logic cores (PLCs) have become available for systems on a chip (SOCs). We describe a novel highspeed PLC architecture. By combining a high-performance dynami...Show MoreMetadata
Abstract:
Programmable logic cores (PLCs) have become available for systems on a chip (SOCs). We describe a novel highspeed PLC architecture. By combining a high-performance dynamic logic style (output prediction logic or OPL), wired-OR structures, a unidirectional routing flow and a product-term-based structure, this architecture achieves an average speedup of 5.7 times over commercial look-up-table (LUT) based architectures using static CMOS. Experimental results for a prototype block fabricated in the TSMC 0.18 /spl mu/m/1.8 V CMOS process are presented.
Published in: Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)
Date of Conference: 06-06 October 2004
Date Added to IEEE Xplore: 22 November 2004
Print ISBN:0-7803-8495-4