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8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3/sup rd/ order, 3/5-bit IIR and 3/sup rd/ order 3-bit-FIR noise shapers in 90nm CMOS | IEEE Conference Publication | IEEE Xplore

8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3/sup rd/ order, 3/5-bit IIR and 3/sup rd/ order 3-bit-FIR noise shapers in 90nm CMOS


Abstract:

This paper describes a fully integrated 8 GHz fractional-n synthesizer with an LC-VCO implemented in a 90 nm CMOS process. The synthesizer incorporates a combination of c...Show More

Abstract:

This paper describes a fully integrated 8 GHz fractional-n synthesizer with an LC-VCO implemented in a 90 nm CMOS process. The synthesizer incorporates a combination of coarse and fine tuning for the VCO, along with a new frequency calibration circuit based on a digital quadri-correlator. This paper derives an integration friendly 3/sup rd/ order 3/5-bit noise shaper from a 6/sup th/ order loop gain. It is jointly optimized with the PLL parameters for low quantization phase noise. This synthesizer has a 1.25 GHz tuning range, 10 kHz resolution, a 20 /spl mu/s settling time, a reference sideband power below the noise floor and a phase noise of -100 dBc/Hz, -117dBc, -145dBc/Hz at 10 kHz, 1 MHz, 20 MHz from the carrier, respectively, and all fractional spurs below -60 dBc. The integrated in-band quantization noise is lower than -64 dBc (well below the other noise sources) and is 10 dB better than a 3rd order MASH implemented in the same process.
Date of Conference: 06-06 October 2004
Date Added to IEEE Xplore: 22 November 2004
Print ISBN:0-7803-8495-4
Conference Location: Orlando, FL, USA

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