Abstract:
We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process...Show MoreMetadata
Abstract:
We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32 times 32 test array implemented in a 130 nm process.
Published in: 2008 IEEE Custom Integrated Circuits Conference
Date of Conference: 21-24 September 2008
Date Added to IEEE Xplore: 17 November 2008
ISBN Information: