Abstract:
Based on a novel two-dimension array architecture, a 1.8 V 0.44 mm2 1 Kbits embedded non-volatile random access memory (NVRAM) IP is developed with 0.18 mum standard logi...Show MoreMetadata
Abstract:
Based on a novel two-dimension array architecture, a 1.8 V 0.44 mm2 1 Kbits embedded non-volatile random access memory (NVRAM) IP is developed with 0.18 mum standard logic CMOS process. Several high voltage solutions and circuits are proposed to improve the reliability and safety of the system. Furthermore, the power consumption for read and write operations are controlled under 312 muA and 88 muA respectively. The merits make it suitable for low power RFID application.
Published in: 2008 IEEE Custom Integrated Circuits Conference
Date of Conference: 21-24 September 2008
Date Added to IEEE Xplore: 17 November 2008
ISBN Information: