A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS | IEEE Conference Publication | IEEE Xplore

A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS


Abstract:

A 10b 210MS/s two-step ADC has been implemented in 0.13μm digital CMOS with an active area of 0.38mm2. Using a proposed capacitor network implemented with small value int...Show More

Abstract:

A 10b 210MS/s two-step ADC has been implemented in 0.13μm digital CMOS with an active area of 0.38mm2. Using a proposed capacitor network implemented with small value interconnect capacitors which replaces the resistor ladder/multiplexer in conventional sub-ranging ADCs, and proposed offset canceling comparators, it achieves 74dB SFDR/55dB SNDR for 10MHz and 71dB SFDR/52dB SNDR for 100MHz inputs at 210MS/s while consuming 52mW from a 1.2V supply.
Date of Conference: 21-24 September 2008
Date Added to IEEE Xplore: 17 November 2008
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Conference Location: San Jose, CA, USA

References

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