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Robust ultra-low voltage ROM design | IEEE Conference Publication | IEEE Xplore

Robust ultra-low voltage ROM design


Abstract:

SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can all...Show More

Abstract:

SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging as the supply voltage is reduced aggressively. In this paper, three different ROM topologies are investigated and compared for ultra-low voltage operation. A simple method to estimate the theoretical robustness at low voltage is proposed and applied to the ROM topologies. A test circuit fabricated in a carefully-selected 0.18μm CMOS technology reveals that our proposed static NAND ROM structure improves performance by 26X, energy by 3.8X and lowest functional supply voltage by 100mV over a conventional dynamic NAND ROM.
Date of Conference: 21-24 September 2008
Date Added to IEEE Xplore: 17 November 2008
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Conference Location: San Jose, CA, USA

References

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