A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction | IEEE Conference Publication | IEEE Xplore

A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction


Abstract:

This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL archit...Show More

Abstract:

This paper describes the design and implementation of a 8times5 Gb/s source-synchronous receiver in a 0.13 mum CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mismatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.
Date of Conference: 21-24 September 2008
Date Added to IEEE Xplore: 17 November 2008
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Conference Location: San Jose, CA, USA

References

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