Discrete-time, cyclostationary phase-locked loop model for jitter analysis | IEEE Conference Publication | IEEE Xplore

Discrete-time, cyclostationary phase-locked loop model for jitter analysis


Abstract:

Timing jitter is one of the most significant phase-locked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to...Show More

Abstract:

Timing jitter is one of the most significant phase-locked loop characteristics, with high impact on performance in a range of applications. It is, therefore, important to develop the tools necessary to study and predict PLL jitter performance at design time. In this paper a discrete-time, linear, cyclostationary PLL model for jitter analysis is proposed, which accounts for the cyclostationary nature of noise injected into the loop at various PLL components. The model also predicts the aliasing of jitter due to the downsampling and upsampling of frequencies around the PLL loop. Closed-form expressions are derived for the output jitter spectrum and match well with results of event-driven simulations of a 3rd-order PLL.
Date of Conference: 13-16 September 2009
Date Added to IEEE Xplore: 09 October 2009
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Conference Location: San Jose, CA, USA

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