The impact of contacts on device and circuit performance is becoming larger with technology scaling because of higher resistance as well as increased variability. Thus, techniques are needed for measurement, analysis, and modeling of variation in contacts, and for devices, interconnects, and circuits in general, in order to ensure robust circuit design. A test chip for characterizing contact plug resistance variability is designed in a 90 nm CMOS process. Each chip is capable of characterizing over 35,000 devices under test. Statistical analysis of the measurement results show that the contact plug resistance changes as a function of key layout parameters, such as the distance from the contact to the polysilicon gate and the distance from the contact to the edge of the diffusion region. Spatial variation analysis shows that the resistance distribution has a systematic die-to-die pattern, possibly caused by variability in the lithography process. Spatial correlation analysis is also performed to identify the possibility of additional systematic trends or separation-distance dependent correlated random variation. Results of these analyses motivate the need for both numerical and compact models for contacts which incorporate variability information.