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47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking | IEEE Conference Publication | IEEE Xplore

47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stacking


Abstract:

An inductive-coupling programmable bus is developed for NAND flash memory access in Solid State Drive (SSD). A channel arrangement scheme using 3 coils enables random acc...Show More

Abstract:

An inductive-coupling programmable bus is developed for NAND flash memory access in Solid State Drive (SSD). A channel arrangement scheme using 3 coils enables random access for memory read and memory write. Transmission power is reduced by 47% compared to a previous design with 2 coils and a shield. A coil layout style, namely XY coil, allows the coils covered by logic interconnections, resulting in area reduction by 91%. Relayed data transmission at 1.6 Gb/s and BER<10-12 is achieved.
Date of Conference: 13-16 September 2009
Date Added to IEEE Xplore: 09 October 2009
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Conference Location: San Jose, CA, USA

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