Abstract:
An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in...Show MoreMetadata
Abstract:
An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the max-log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90 nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92 mm2 can achieve 30 Mb/s with 23.4 mW power consumption.
Published in: 2009 IEEE Custom Integrated Circuits Conference
Date of Conference: 13-16 September 2009
Date Added to IEEE Xplore: 09 October 2009
ISBN Information: