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Analysis and demonstration of MEM-relay power gating | IEEE Conference Publication | IEEE Xplore

Analysis and demonstration of MEM-relay power gating


Abstract:

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with today's relatively large, high-voltage mic...Show More

Abstract:

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with today's relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.
Date of Conference: 19-22 September 2010
Date Added to IEEE Xplore: 01 November 2010
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Conference Location: San Jose, CA, USA

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