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A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS | IEEE Conference Publication | IEEE Xplore

A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS


Abstract:

A stacked amplifier architecture has been used to achieve high RF output power levels in sub-100nm CMOS. The stacking makes it possible to both operate the power amplifie...Show More

Abstract:

A stacked amplifier architecture has been used to achieve high RF output power levels in sub-100nm CMOS. The stacking makes it possible to both operate the power amplifier (PA) from a large supply voltage and implement RF power combining. As a proof of concept, a 6.5-GHz PA has been integrated in a 65-nm standard CMOS technology. The amplifier achieves 27.4-dBm output power with an efficiency of 19.2% at 6.5 GHz when driven from a 3.6-V supply voltage and 29.6-dBm output power with an efficiency of 20.3%, when driven from a 4.6-V supply voltage.
Date of Conference: 19-22 September 2010
Date Added to IEEE Xplore: 01 November 2010
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Conference Location: San Jose, CA, USA

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