A multi-GHz area-efficient comparator with dynamic offset cancellation | IEEE Conference Publication | IEEE Xplore

A multi-GHz area-efficient comparator with dynamic offset cancellation


Abstract:

In this paper we propose a dynamic impedance modulation technique to significantly improve the speed of comparators utilizing dynamic-offset-cancellation (DOC). Measureme...Show More

Abstract:

In this paper we propose a dynamic impedance modulation technique to significantly improve the speed of comparators utilizing dynamic-offset-cancellation (DOC). Measurements from a 65nm test-chip show that DOC comparators utilizing the proposed technique achieve 6X lower input-referred offset and 9X better power supply noise rejection than a traditional StrongArm comparator with only a 20% speed penalty at identical core comparator area (98µm2) while dissipating 455µW.
Date of Conference: 19-21 September 2011
Date Added to IEEE Xplore: 20 October 2011
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Conference Location: San Jose, CA, USA

References

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