Abstract:
A continuous-rate CDR based upon a digital dual delay/phase locked loop is reported. This CDR is implemented in 0.13μm CMOS and operates from 6.5Mb/s to 11.3Gb/s. It exce...Show MoreMetadata
Abstract:
A continuous-rate CDR based upon a digital dual delay/phase locked loop is reported. This CDR is implemented in 0.13μm CMOS and operates from 6.5Mb/s to 11.3Gb/s. It exceeds all SONET jitter specifications from OC-3 to OC-192, with random jitter of 452fs at 9.95Gb/s. The die area is 2×2mm2, and is implemented in a 24-pin LFCSP.
Date of Conference: 15-17 September 2014
Date Added to IEEE Xplore: 06 November 2014
Electronic ISBN:978-1-4799-3286-3
Contents 