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Design Technology co-optimization for N10 | IEEE Conference Publication | IEEE Xplore

Design Technology co-optimization for N10


Abstract:

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as devi...Show More

Abstract:

Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in the development of a technology node. This design assessment and decisions start from lithography constraints and options to power/performance, area and cost, all of which create the Design-Technology Co-Optimization space.
Date of Conference: 15-17 September 2014
Date Added to IEEE Xplore: 06 November 2014
Electronic ISBN:978-1-4799-3286-3

ISSN Information:

Conference Location: San Jose, CA, USA

References

References is not available for this document.