This paper describes the implications of Bias Temperature Instability (BTI) related time-dependent threshold voltage distributions on the performance and yield of devices and SRAM cells. We show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced technology. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The assumption of Normally distributed threshold voltages, imposed by State-of-the-Art design approaches, is shown to induce inaccuracy which is readily solved by adopting our defect-centric statistical approach.