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A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier | IEEE Conference Publication | IEEE Xplore

A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifier


Abstract:

Ring amplifiers have emerged as a scalable amplification technique. This work is a ring amplifier built with current-starved inverters in the intermediate stage. This str...Show More

Abstract:

Ring amplifiers have emerged as a scalable amplification technique. This work is a ring amplifier built with current-starved inverters in the intermediate stage. This structure allows for the implementation of a dynamic deadzone that allows a single amplifier to perform both coarse estimation and fine settling. A pipelined ADC with a sampling speed of 20 MSPS is implemented in 0.18um CMOS. The ADC consumes 2.74 mW and achieves a peak SNDR of 74.33 dB which provides a FoM of 32.2 fJ/c-step with no calibration required.
Date of Conference: 30 April 2017 - 03 May 2017
Date Added to IEEE Xplore: 27 July 2017
ISBN Information:
Electronic ISSN: 2152-3630
Conference Location: Austin, TX, USA

References

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