Abstract:
The design of power-efficient ADCs able to achieve both high linearity and bandwidth in deep nanoscale CMOS processes becomes very challenging as the constraints of lowvo...Show MoreMetadata
Abstract:
The design of power-efficient ADCs able to achieve both high linearity and bandwidth in deep nanoscale CMOS processes becomes very challenging as the constraints of lowvoltage operation and limited intrinsic gain often mandate the use of power-consuming analog circuits and digital calibration. This work introduces a pipelined ADC that leverages the low but very flat open-loop gain vs. output swing characteristic of the ring amplifier (ringamp) to address these problems. A 12-bit, 1Gsps, single-channel prototype is implemented in a 28nm planar CMOS process achieving 56.6dB SNDR and 73.1dB SFDR. Consuming 24.8mW from a single 0.9V supply, it achieves Schreier and Walden FoMs of 159.6dB and 45fJ/conv.-step, respectively.
Published in: 2018 IEEE Custom Integrated Circuits Conference (CICC)
Date of Conference: 08-11 April 2018
Date Added to IEEE Xplore: 10 May 2018
ISBN Information:
Electronic ISSN: 2152-3630