In this paper a novel technique is introduced to extract the quantization noise of a multi-phase VCO-based quantizer (VCOQ) in the time domain as a PWM signal. Using this technique, a new highly linear VCO-based 1-1 MASH delta-sigma ADC structure is presented. This architecture does not require any OTA-based analog integrators or power hungry linearization methods. The first stage is a closed loop multi-phase VCO-based voltage-to-phase (V-to-P) converter and the second stage is an open loop multi-phase VCO-based voltage-to-frequency (V-to-F) converter. Using the proposed technique the phase quantization error of the first stage is extracted as a pulse signal and then fed to the second stage. The input of the first VCO is a very small amplitude signal and the input of the second VCO is a two-level PWM signal. Therefore, the VCO non-linearity does not limit the overall ADC performance, mitigating the need for power hungry linearization methods. The prototype achieves 2^nd order noise shaping with a DR/SFDR/SNR/SNDR of 82.7/88.7/80.3/79.7 dB for an input signal BW of 2 MHz. The fabricated design consumes 1.248 mW from a 0.9 V. supply.