This work implements a 3mW 6b 4GS/s subranging ADC in 28nm CMOS. With the proposed adaptive offset-adjustable comparators (OACs), the subranging architecture is free of both conventional reference-voltage switching to increase speed and the resistor ladder to save power. A proposed calibration technique mitigates the intrinsic offset of the OACs and improves the linearity of the fine ADC in different subrange regions. At 3.6GS/s, the ADC has the best Walden FOM of 22.7fJ/conv-step compared with prior state-of-the-art ADCs.