A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET | IEEE Conference Publication | IEEE Xplore

A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET


Abstract:

A multi-lane short-reach wireline transceiver is implemented in 16nm FinFET. Taking advantage of a low-loss channel with minimum reflections, 56Gbps NRZ differential sign...Show More

Abstract:

A multi-lane short-reach wireline transceiver is implemented in 16nm FinFET. Taking advantage of a low-loss channel with minimum reflections, 56Gbps NRZ differential signaling is employed, using only a continuous time linear equalizer (CTLE) in the receiver to perform equalization. The transceiver incorporates low swing signaling, a central PLL with regulated CMOS clock distribution, and an injection-locked oscillator (ILO)-based per-lane skew adjustment. At the system level, a common reference clock is used to increase link margin through jitter tracking. The transceiver achieves a BER of <;1e-15 over a channel with 8dB loss at 28GHz with an efficiency of 2.25pJ/bit.
Date of Conference: 14-17 April 2019
Date Added to IEEE Xplore: 01 August 2019
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Conference Location: Austin, TX, USA

References

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