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A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer | IEEE Conference Publication | IEEE Xplore

A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer


Abstract:

This work presents an Advanced Interface Bus (AIB)-compatible microcontroller unit (MCU) chiplet in 16nm FinFET CMOS. The MCU chiplet consists of three AIB channels, each...Show More

Abstract:

This work presents an Advanced Interface Bus (AIB)-compatible microcontroller unit (MCU) chiplet in 16nm FinFET CMOS. The MCU chiplet consists of three AIB channels, each providing 20 Tx and Rx pairs to support 80Gb/s/channel over 55μm - pitch microbumps. Two multi-chip modules (MCM) were constructed, one made of two MCU chiplets integrated on a 180nm passive silicon interposer, and the other made by pairing an MCU chiplet with a Stratix 10 FPGA over an Embedded Multi-die Interconnect Bridge (EMIB). The AIB interface provides 256Gb/s/mm-shoreline, consuming 0.83pJ/b at 0.9V and 1GHz. The two MCMs demonstrate the ease and versatility of modular 2.5D integration.
Date of Conference: 25-30 April 2021
Date Added to IEEE Xplore: 17 May 2021
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Conference Location: Austin, TX, USA

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