Abstract:
As well as low jitter performance, modern wireless communication standards also require low-spurious PLLs, since spurs cause the violation of emission masks and worse int...Show MoreMetadata
Abstract:
As well as low jitter performance, modern wireless communication standards also require low-spurious PLLs, since spurs cause the violation of emission masks and worse inter-carrier interference (ICI) in OFDM systems like 5G. Cascaded PLLs have been recently exploited for low-jitter frequency synthesis with a large frequency multiplication ratio N [1]. Previous fractional cascaded PLLs use a 1st-stage fractional-N PLL and a 2nd-stage integer-N PLL [2] or a 1st stage integer-N PLL and a 2nd-stage fractional-N PLL [3]. Similar to single-stage PLLs, fractional spurs are degraded at near-integer channels in the conventional cascaded PLLs since those spurs appear at too low offset frequencies to be filtered by PLL loop function. To meet the ever-growing demand on low spur levels, the fractional spurs in cascaded PLLs must be suppressed.
Published in: 2023 IEEE Custom Integrated Circuits Conference (CICC)
Date of Conference: 23-26 April 2023
Date Added to IEEE Xplore: 11 May 2023
ISBN Information: