Modern electronic systems demand a more and more complex data modulation scheme along with higher and higher spectral efficiency, which manifests the importance of a fractional-N PLL with ultra-low rms jitter to provide an agile and pure local oscillator signal with arbitrary frequency. For the frequency agility requirement, the charge pump PLL (CPPLL) is well-known for its robustness. For noise consideration, the noise of charge pump (CP) and the quantization error (OE) of delta-sigma modulator (DSM) are two of the main contributors in the fractional-N CPPLLs. To deal with the noise of CP, recent work in [1] presented a CPPLL with time-amplifying-phase-frequency detector (TAPFD) to suppress the input-referred noise of CP. However, the linear range limitation of TAPFD prohibits its direct application to a fractional-N PLL. To cancel the OE of DSM, a digital-to-time converter (DTC) is usually employed [2] [3]. Nevertheless, a DTC with low noise, good linearity and fine resolution remains the most challenging block in the fractional-N PLL for ultra-low jitter (e.g., sub-50fs) and low fractional spurs.