As the advanced process and shrinking feature size integrate more and more functions on one chip, accompaniments are problems of lithography and material defects affecting the yield and quality of the chip beyond nanometer process. Via defects and congested wires are not beneficial for manufacturing in clock network and they should be avoided in the design. In this paper, we refine these defects by layer assignment and formulate this assigning problem as conflict graph. The conflict graph is solved by maximum independent sets in each layer recursively and experimental results show almost 82% reduction rate of vias and 100% avoidance of all wires suffered in serious optical proximity effect in X architecture clock tree.