Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache | IEEE Conference Publication | IEEE Xplore

Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache

Publisher: IEEE

Abstract:

On-chip DRAM cache has the advantage of increased cache capacity that may alleviate the memory bandwidth problem. Recent research has demonstrated the benefits of high ca...View more

Abstract:

On-chip DRAM cache has the advantage of increased cache capacity that may alleviate the memory bandwidth problem. Recent research has demonstrated the benefits of high capacity on-chip DRAM cache that leads to reduced off-chip accesses. However, state-of-the-art has not taken into consideration the cache access patterns of concurrently running heterogeneous applications that can cause inter-core cache contention. We therefore propose an adaptive bank mapping policy in response to the diverse requirements of applications with different cache access behaviors that - as a result - reduces inter-core cache contention in DRAM-based cache architectures. On average, our adaptive bank mapping policy increases the harmonic mean instruction-per-cycle throughput by 19.3% (max. 71%) compared to state-of-the-art bank mapping policies.
Date of Conference: 29 September 2013 - 04 October 2013
Date Added to IEEE Xplore: 11 November 2013
Electronic ISBN:978-1-4799-1417-3
Publisher: IEEE
Conference Location: Montreal, QC, Canada

References

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