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Towards the Automatic Implementation of Reduced-size and High Throughput MPC on FPGAs | IEEE Conference Publication | IEEE Xplore

Towards the Automatic Implementation of Reduced-size and High Throughput MPC on FPGAs


Abstract:

The implementation of model predictive controllers on resource-constrained embedded platforms requires fast and computationally efficient processors to solve constrained ...Show More

Abstract:

The implementation of model predictive controllers on resource-constrained embedded platforms requires fast and computationally efficient processors to solve constrained convex optimization problems. We propose a set of design rules that make use of both, analytical guidelines and numerical simulations to achieve fixed-point implementations of an efficient interior-point (IP) algorithm for solving quadratic-programming (QP) problems. This is the first an necessary step in the development of a complete semiautomatic tool for the implemention of hardware accelerated predictive controllers for embedded and high throughput applications.
Date of Conference: 23-26 April 2019
Date Added to IEEE Xplore: 02 September 2019
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Conference Location: Paris, France

References

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