This paper presents a 10-bit 5 MS/s low-power single-ended successive approximation register (SAR) ADC with an optimized low-power switching scheme for low/zero IF receiver application. By introducing a second reference voltage as well as the bridge capacitor, the total capacitance and resolution of the CDAC can be reduced. Therefore, the single-ended SAR ADC has less switching power consumption. Implemented in 0.13 µm BiCMOS technology, the core of the ADC occupies an area of 0.16 mm² and consumes 117 µW (excluding Buffers) from a 1.2V supply. Post-layout simulation results shows that the ADC can operate at 5 MS/s with a 65 MHz clock. The ADC can achieve a SFDR of 71.7dB with a FOM of 26.6fJ/conversion-step at 5 MS/s.