Abstract:
3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scal...Show MoreMetadata
Abstract:
3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra-wide inter-chip connection technology that enables systems to have lower power consumption, higher scalability in its functionality and performance just by increasing the number/type of chips, allows to be manufactured with much more flexibility, and has a better cost/performance than conventional 2D SoC based designs.
Published in: 2011 IEEE Cool Chips XIV
Date of Conference: 20-22 April 2011
Date Added to IEEE Xplore: 16 June 2011
ISBN Information: