Abstract:
This paper describes the implementation of a graphic rendering pipeline on an MPSoC architecture devoted to the dynamic management of static task graphs. It exhibits the ...Show MoreMetadata
Abstract:
This paper describes the implementation of a graphic rendering pipeline on an MPSoC architecture devoted to the dynamic management of static task graphs. It exhibits the highly non stationary workloads of this application domain and provides first useful feedbacks motivating the design of innovative embedded architectures that have to face heterogeneous computation domains such as graphics and telecommunications. Especially these experiments stress the needs for data dependent resource allocation strategies.
Published in: Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)
Date of Conference: 02-04 November 2011
Date Added to IEEE Xplore: 23 January 2012
ISBN Information: