The rapid pace of change in IC technology, specifically in speed of operation, demands sophisticated design solutions for IC testing methodologies. Moreover, the current technology of system-on-chip (SOC) makes great demands for testing internal speed accurately as the limitation on accessing internal nodes using I/O pins becomes more difficult. This paper presents two high-resolution time measurement schemes for digital BIST applications, namely: two-delay interpolation method (TDIM) and time amplifier. The two schemes are combined to produce a completely new design for BIST time measurement which offers two main advantages: a low range of timing measurement which has never been achieved before, and a small size of layout occupying 0.2 mm/sup 2/ or equivalent to 3020 transistors. These two features are undoubtedly compatible with present high-speed SOC design architectures.