Modern FPGAs contain on-chip synchronous embedded memory blocks (SEMBs), these memory blocks can be used to implement control units, when not used as on-chip memory. In this paper, we explore the mapping of finite state machines (FSMs) into the SEMBs for power and area minimization. We have shown the SEMB based implementation of the FSMs and compared it with conventional flip-flop (FF) based implementation. The proposed implementation of the FSMs consumes less power and has lower area and routing overhead than the FF based approach and it can be clocked at the maximum clock frequency supported by the SEMBs. Experimental results show that the SEMB based FSM consumes 4% to 26% less power than the conventional implementation. In addition it is observed that the power consumption can be further reduced by stopping the clock to the SEMBs during the idle states.