Abstract:
This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis flow using these parasitic mod...Show MoreMetadata
Abstract:
This paper presents efficient and accurate techniques for modeling parasitic capacitances in analog CMOS circuits. A layout aware synthesis flow using these parasitic models has been proposed. The fast parasitic estimation process replaces the time consuming steps of layout generation and extraction during synthesis. Results indicate that these models are extremely fast and accurate.
Date of Conference: 16-20 February 2004
Date Added to IEEE Xplore: 08 March 2004
Print ISBN:0-7695-2085-5
Print ISSN: 1530-1591