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Approximate logic circuits for low overhead, non-intrusive concurrent error detection | IEEE Conference Publication | IEEE Xplore

Approximate logic circuits for low overhead, non-intrusive concurrent error detection


Abstract:

This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent e...Show More

Abstract:

This paper describes a scalable, technology-independent algorithm for the synthesis of approximate logic circuits. A low overhead, non-intrusive solution for concurrent error detection (CED) based on such circuits is described in this paper. CED based on approximate logic circuits does not impose any performance penalty on the original design. The proposed synthesis algorithm for approximate logic circuits scales with circuit size, and provides fine-grained trade-offs between area-power overhead and CED coverage.
Date of Conference: 10-14 March 2008
Date Added to IEEE Xplore: 11 April 2008
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Conference Location: Munich, Germany

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